-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024
-- Date        : Thu Nov  6 20:01:06 2025
-- Host        : DESKTOP-IL2I0O0 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode synth_stub
--               d:/programs/FPGA/multi_lia_pipline_ds/multi_lia_pipline_ds.gen/sources_1/ip/IIR_2_core_pipline_0/IIR_2_core_pipline_0_stub.vhdl
-- Design      : IIR_2_core_pipline_0
-- Purpose     : Stub declaration of top-level module interface
-- Device      : xc7a35tfgg484-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity IIR_2_core_pipline_0 is
  Port ( 
    clk : in STD_LOGIC;
    rst_n : in STD_LOGIC;
    en_flag : in STD_LOGIC;
    busy : out STD_LOGIC;
    next_en_flag : out STD_LOGIC;
    datin_bram_r_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    datin_bram_r_en : out STD_LOGIC;
    datin_bram_r_addr : out STD_LOGIC_VECTOR ( 11 downto 0 );
    daout_bram_w_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    daout_bram_w_we : out STD_LOGIC;
    daout_bram_w_en : out STD_LOGIC;
    daout_bram_w_addr : out STD_LOGIC_VECTOR ( 11 downto 0 )
  );

end IIR_2_core_pipline_0;

architecture stub of IIR_2_core_pipline_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst_n,en_flag,busy,next_en_flag,datin_bram_r_data[15:0],datin_bram_r_en,datin_bram_r_addr[11:0],daout_bram_w_data[15:0],daout_bram_w_we,daout_bram_w_en,daout_bram_w_addr[11:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "IIR_2_core_pipline,Vivado 2024.1";
begin
end;
